This invention relates, in general, to MOS transistors, and more particularly, to MOS transistors having a source characterized by low barrier height and low minority carrier injection.
A conventional MOS transistor includes spaced apart source and drain regions formed in a body of semiconductor material. The surface of the semiconductor body between the source and drain regions forms the channel of the transistor. The conductivity of the channel is modulated by the potential on a gate electrode which overlies but is insulated from the semiconductor body. In an N channel MOS transistor, for example, the body of semiconductor material is P type and the source and drain regions are N type regions formed in the body, typically by diffusion, ion implantation, or the like. So formed, the source and drain regions form rectifying PN junctions with the semiconductor body. The term "MOS transistor" is herein used to mean any of the insulated gate field effect transistors regardless of the material used for the gate electrode or gate insulator.
In addition to functioning as a normal MOS transistor, this structure also functions as a particular bippolar transistor with the source, body or channel, and drain functionimg as emittter, base, and collector, respectively. The parasitic bipolar transistor can have adverse effects on the operation of the MOS transistor. If the emitter-base junction of the parasitic bipolar transistor is forwad biased so that the parasiic transistor becomes operative, this can have two undesirable effects on the operation of the MOS transistor. First, the operation of the parasitic bipolar transistor results in the injection of minority carriers into the base of the parasitic device from the emitter. In order to turn off the combination of MOS transistor and parasitic bipolar transistor it is then necessary to sweep these minority carriers out of the base region before the combination of devices is effectively turned off. The time required for sweeping out these minority carriers adversely affects the switching speed of the MOS transistor. The MOS transistor, being a majority carrier device, is generally considered to have an inherently fast switching speed, but the presence of the parasitic bipolar transistor degrades the switching performance so that the inherent speed is not achieved.
Second, the presence of the parasitic bipolar transistor in parallel with the MOS transistor also adversely affects the breakdown performance of the device, especially when the device is used with an inductive load. If the bipolar transistor turns on, the breakdown of the two devices in parallel is dominated by the breakdown of the bipolar transistor in the BV.sub.CEO mode. This breakdown is normally much lower than the drain to source breakdown of the MOS transistor, BV.sub.DSS. The breakdown voltage problem is especially severe when switching inductive loads, and results in a degradation of safe operating area (SOA) of the device. BV.sub.CEO of the bipolar transistor is inversely proportional to the beta of the transistor. Unfortunately, the beta of the parasitic transistor is likely to be quite high, especially with short channel MOS transistors, because of the small amount of doping in the channel region or parasitic base region. Beta cannot easily be reduced to improve on the breakdown problem; beta is dependent upon doping, but the threshold voltage of the MOS transistor is also dependent on this doping and threshold voltage must be controlled to meet the operating requirements of the device. Beta, and thus the BV.sub.CEO of the parasitic transistor, therefore cannot be arbitrarily controlled by altering the doping characteristics of the device.
In an attempt to counter these adverse effects, in operating the MOS transistor the source-body potential is controlled and is typically maintained at zero volts. That is, the source and body are electrically shorted together in order to short the emitter and base thereby disabling the parasitic transistor. Because of current flowing through the body or channel of the MOS transistor, however, an internal bias is generated within the device which may be sufficient to forward bias the emitter-base junction of the parasitic transistor despite the intended short circuit.
In some MOS transistors the body of the device is contacted on the back surface of the semiconductor chip. In other devices, such as diffused channel MOS transistors, the body and channel regions are diffused into the top surface of the semiconductor wafer and the source region is then formed within the diffused region. An electrical short between source and channel or body must then be effected on the top surface of the device by metal overlapping the source and body. This usually requires an additional heavily doped contact diffusion to insure good ohmic contact between the metal and the diffused body. The use of a contact diffusion requires additional space and, therefore, decreases the density of MOS transistors that can be achieved. This loss in density is in addition to the above mentioned problems with a parasitic bipolar transistor formed in parallel with the intended MOS transistor.
In view of the foregoing, it is apparent that it would be desirable to provide an improved MOS transistor and method for making that transistor which would overcome the above related and other problems.
Accordingly, it is an object of the present invention to provide an improved MOS transistor having increased switching speeds.
It is another object of this invention to provide an improved MOS transistor having improved safe operating area.
It is yet another object of this invention to provide an improved and higher density MOS transistor.
It is still another object of this invention to provide an improved method for forming an MOS transistor.